1. Field of the Invention
This invention relates to fault tolerant circuit arrangements which may be used, for example, for the drive circuitry of active matrix liquid crystal displays (AMLCD).
2. Description of the Related Art
In recent years there has been considerable interest in the fabrication of integrated circuits on glass substrates using thin film transistors. The main reason for such interest has been the desire to integrate the drive circuitry of AMLCD's onto the glass substrate of the display itself. However such integration of the control circuitry can result in a decrease in the manufacturing yield caused by faults within the integrated drive circuitry. Such integrated drive circuitry is prone to failure as a result of its large area and inherent variation in the properties of the thin film transistors. Variations in parameters, such as the threshold voltage and mobility of the transistors, often manifest themselves as a soft failure caused by the inability of a particular transistor to match the performance of neighboring transistors in the same circuit. For these reasons, fault tolerant circuit design is becoming increasingly important both in AMLCD applications in order to increase the yield of the displays with integrated drive circuitry and also in other large area applications of thin film electronics.
A number of fault tolerant design techniques are already known. Redundancy-with-repair (RWR) involves duplicating the basic functional circuit and employing some means to effect a repair if one of the functional circuits is found to be faulty after manufacture. U.S. Pat. No. 5,111,060 (NEC Corporation) and Y. Takafuji et al, SID 93 Digest, pages 383-386 disclose the application of a RWR technique to AMLCD's. Furthermore FIG. 1 of the accompanying drawings shows a RWR circuit arrangement for the peripheral circuit of an AMLCD in which a number of basic functional circuits are duplicated to form shift register element pairs 1, 1a; 2, 2a; 3, 3a etc., with the spare shift register elements 1, 2, 3, etc. being connected between the associated circuit input and output by means of welding pads 4 and 5 in parallel with the shift register elements 1a, 2a, 3a etc. connected between the associated circuit input and output by means of cutting pads 6 and 7. Thus there is provision for completely removing a defective shift register element, such as 1a, from the circuit by irradiating the cutting pads 6 and 7 with a laser and welding in the replacement shift register element, such as 1, by means of the welding pads 4 and 5. Whilst RWR techniques can offer significant fault tolerance with reasonable overhead and negligible detrimental effect on circuit performance, there are many applications in which the low level test and repair steps of such a technique are too expensive to incorporate in the fabrication process.
Triple modular redundance (TMR) involves replicating the basic functional circuit in triplicate and connecting the outputs of the circuits 10, 11 and 12 to a common voting circuit 13 for producing an output corresponding to the majority vote of the outputs of the circuits 10, 11 and 12, as shown diagrammatically in FIG. 2 of the accompanying drawings. Such a technique is known from C. Bolchini et al, IEEE International Symposium on Circuits and Systems 1994, pages 83-86 and A. A. Sorenson "Digital circuit reliability through redundancy" Electro-Technology, 68, July 1961, pages 118-125. It will be appreciated that such a technique can be implemented by connecting the circuits 10, 11 and 12 to three AND gates driving a common OR gate. Such an arrangement is tolerant to a fault in any one of the three circuits 10, 11 and 12. However there is only a certain probability that such an arrangement will tolerate additional faults. Furthermore the technique is rendered costly by the provision of circuits in triplicate and by the associated decision logic. Furthermore the performance will be considerably inferior to a correctly functioning non-redundant circuit in terms of power consumption and speed, as a result of the additional load presented by the three parallel circuits and also the delay through the decision logic. For these reasons the TMR technique is not practicable for the decision circuits of AMLCD's which are essentially simple replicated circuits required to operate at high speed.
Another technique, which has not received as much attention in the literature, is Quad Masking (QM), such a technique being referred to by R. Kuen. "Computer redundancy:design, performance and future", IEEE Transactions on Reliability, Vol. R-18, No.1, February 1969, pages 3-11. As shown diagrammatically in FIG. 4 of the accompanying drawings, the QM technique involves connecting together four basic functional circuits 15, 16, 17 and 18 such that the circuits 15 and 16 are in series and the circuits 17 and 18 are in series, and the circuit pairs 15, 16 and 17,18 are connected in two parallel paths between a common input and output. Such a technique is considerably more robust than the TMR technique, and at least two of the circuits must fail to cause failure of the arrangement. The connection 19 shown by a broken line in FIG. 4 can be made according to the relative probabilities of occurrence of stuck open (non-conducting) and stuck closed (conducting) faults. If the arrangement is more likely to suffer from stuck open faults, the connection 19 is made since it gives another path through the arrangement. Although this technique is very robust, with only a modest area required for thin film MOS implementation, a circuit arrangement constructed with this type of logic will be considerably slower and will exhibit a higher power consumption than its non-redundant counterpart.
U.S. Pat. No. 5,465,053 discloses a circuit arrangement for driving an AMLCD, as shown diagrammatically In FIG. 3, comprising replicated shift registers of N stages split up into N/n shorter shift registers 70 and 71 each having n stages 72, these shorter shift registers being replicated k times (k=2 in the figure). Thus the circuit arrangement comprises N/n banks of k non-redundant registers each of length n. Furthermore the output of the final stage 72 of each of the shift registers 70, 71 forms ap input to a test/control circuit 73 at the end of each bank which performs a test procedure in which the inputs are compared to a test signal to determine which of the registers is functioning correctly. Furthermore the outputs from the stages 72 of the shift registers 70, 71 are connected to the active matrix by means of k input multiplexers 74 and driver circuits 75. In operation the test/control circuit 73 determines which of the registers 70, 71 is functioning correctly and selects an appropriate one of the registers 70, 71 which is working correctly for addressing of the AMCLD by controlling the multiplexers 74 so as to supply the outputs from the stages 72 of the selected register to the driver circuits 75.
The effectiveness of this type of redundancy, that is the probability that all N outputs from the driver circuits are correct, can be demonstrated by an analysis which assumes that each transistor performs as a simple digital switch with a probability of failure (either stuck open or stuck closed) equal to f, that the entire row within a bank is considered to have failed if any shift register stage within that row fails, that the entire bank is considered to have failed if there is a defect in the support circuitry in a particular bank, and that the entire circuit arrangement is considered to have failed if any bank fails. In this regard the support circuitry is considered to comprise the combination of the test control circuit 73 and the associated multiplexers 74 which each comprise conventional non-redundant TFT circuits.
With these assumptions, the following probabilities can be calculated:
The probability that one transistor works correctly is EQU P(T.sub.ok)=1-f=g
The probability that one latch, with t transistors, is fault free is EQU P(Latch.sub.ok)=g.sup.t 32 l
The probability that a register of an such latches is free from faults is given by: EQU P(Reg.sub.ok)=l.sup.n =r
Therefore the probability that at least one of the k rows in a bank functions correctly is given by: EQU P(Row.sub.ok)=1-(l-r).sup.k =R
The probability that the n k-input multiplexers 74, each with m transistors, all work is given by: EQU P(Mult.sub.ok)=g.sup.nkm =M
The probability that the test/control circuit 34, containing s transistors, is free from faults is given by: EQU P(Control.sub.ok)=g.sup.k =C
Therefore each bank has the following probability of functioning correctly: EQU P(Bank.sub.ok)=P(Row.sub.ok).times.P(Control.sub.ok).times.P(Mult.sub.ok)=R CM
Finally the yield of the entire circuit arrangement comprising N/n such banks is given by: EQU P(Drive.sub.ok)=(RCM).sup.N/n
FIG. 3A shows the yield of the entire circuit arrangement plotted as a function of the number of stages in each bank n and the number of replicated registers in each bank k for a typical circuit arrangement in which the transistor failure rate f=0.01%, the number of columns N=800, the number of transistors per latch is 6, the number of transistors in the test/control circuit 73 is 17(k=2) and the number of transistors in each multiplexer 74 is 1. It is apparent from this graph that the redundant circuit arrangement of U.S. Pat. No. 5,465,053 has a number of limitations which would render the additional circuit complexity of such an arrangement unjustifiable in most applications. Compared with the yield of a corresponding non-redundant circuit arrangement of about 61% as shown in the figure, the best yield obtainable with the circuit arrangement of U.S. Pat. No. 5,465,053 is about 82% (for k=2 and n=50) at the expense of much increased circuit complexity. Furthermore there is very little benefit from increasing the number of rows in each bank since defects in the support circuitry have a significant impact on overall yield. Furthermore the test/control circuit 73 does not test for correct operation of the multiplexers 74.